general purpose register वाक्य
उदाहरण वाक्य
मोबाइल
- Most current computer instruction sets are based on a general purpose register model.
- It had thirty-one 32-bit general purpose registers, but no Alpha.
- CR16 has 16 general purpose registers of 16 bits, and address registers of 21 bits wide.
- For example, the MOS Technology 6502 has only one general purpose register ( the accumulator ).
- It had sixteen 32-bit general purpose registers and used 32-bit addresses and data paths.
- The chip contained seven 8-bit general purpose registers, although only four were visible at any time.
- Generally accepted standards, although by no means mandatory, include the identification of general purpose registers with mnemonics.
- Virtual addresses 0 thru 15 are reserved to reference the corresponding general purpose register, and are not mapped.
- The particular address in the list of addresses may be extracted using an index, general purpose register or pointer.
- The subroutine typically requires standard function prologue and epilogue usually saving general purpose registers and return address as a minimum ).
- General purpose registers were normally located in a non-addressable portion of 1 ?s core storage termed " bump storage ".
- MAX instructions operate on 32-or 64-bit SIMD data types consisting of multiple 16-bit integers packed in general purpose registers.
- Modern computer systems often have multiple general purpose registers that operate as accumulators, and the term is no longer as common as it once was.
- Similarly, pointers and indirect addressing use the X register ( SEX Rn instruction ), or the 16 registers can be used as general purpose registers.
- For added speed, the general purpose registers could be implemented in Solid Logic Technology ( SLT ) circuitry with an access time of . 25 ?s.
- The additional operands specify which one of many general purpose registers ( also called " general purpose accumulators " ) are used as the source and destination for calculations.
- Such machines either do not pass " implicit " status information between instructions at all, or they pass it in an explicitly selected general purpose register.
- The TMS34010 is a bit addressable, 32-bit processor, with two register files, each with fifteen general purpose registers and sharing a sixteenth stack pointer register.
- Each processor, in addition to the PSW queue and instruction pipeline, contained instruction memory, 2, 048 64-bit general purpose registers and 4, 096 constant registers.
- AVX's three-operand format is limited to the instructions with SIMD operands ( YMM ), and does not include instructions with general purpose registers ( e . g.
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